Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same

ABSTRACT

A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to integrated circuit (IC) packages, andmore particularly, to a dual-chip integrated circuit package withunaligned chip arrangement and a method of manufacturing such adual-chip integrated circuit package.

[0003] 2. Description of Related Art

[0004] A DIP (Dual In-Line Package) is a type of integrated circuitpackage that includes a metal leadframe with a die pad and a pluralityof leads. An integrated circuit chip is mounted on the die pad andelectrically connected via a set of conductive wires to the leads, andan encapsulant is formed to encapsulate the entire integrated circuitchip, the entire die pad, and part of the lead fingers therein so as toallow easy handling and utilization of the integrated circuit packageand to protect the enclosed integrated circuit chip from beingcontaminated or damaged by outside objects.

[0005] In the design and manufacture, it is usually desired to mount asmany integrated circuit chips in a single integrated circuit package aspossible so as to allow one single integrated circuit package to offermore functions. An integrated circuit package that packs two integratedcircuit chips therein is customarily referred to as a dual-chipintegrated circuit package. Since a dual-chip integrated circuit packagepacks two integrated circuit chips rather than just one, it can helpsave layout space on the circuit board and offers more functionality andstorage capacity. A conventional dual-chip integrated circuit package isdisclosed in U.S. Pat. No. 5,012,323, whose structure is brieflydescribed in the following with reference to FIGS. 8-10.

[0006] As shown in FIG. 8, the U.S. Pat. No. 5,012,323 utilizes adual-row lead-frame 21 which includes a left part and a right part (asdelimited by the dashed line 25). The left part includes a set ofleft-outer leads 23LO and a set of left-inner leads 23LI, while theright part includes a set of right-outer leads 23RO and a set ofright-inner leads 23RI. Further, the left part is formed with a leftslot 26L between the left-outer leads 23LO and the left-inner leads 23LI(as the area enclosed in the dashed box), while the right part is formedwith a right slot 26R between the right-outer leads 23RO and theright-inner leads 23RI (as the area enclosed in the dashed box). Thedual-chip integrated circuit package is used to pack two integratedcircuit chips therein, including an upper die 41 and a lower die 43, asshown in FIGS. 9 and 10. The lower die 43 has its top side attached bymeans of an insulative adhesive layer 44 on the bottom side of theleft-inner leads 23LI and the right-inner leads 23RI, while the upperdie 41 has its back side attached by means of another insulativeadhesive layer 42 on the upper side of the left-inner leads 23LI and theright-inner leads 23RI. As illustrated in FIGS. 9 and 10, the lower die43 should be greater in size than the upper die 41 so as to allow theleft side 43L and the right side 43R of the lower die 43 to extendrespectively into the left slot 26L and the right slot 26R; and thelength from the left side 41L to the right side 41R of the upper die 41should be less than the distance between the left slot 26L and the rightslot 26R so as to facilitate the wire-bonding process for electricallyconnecting the bonding pads 43LP and 43RP via the bonding wires 47 tothe left-outer leads 23LO, the left-inner leads 23LI, the right-outerleads 23RO, and the right-inner leads 23RI. In a similar manner, thebonding pads 41LP, 41RP on the left side 41L and the right side 41R ofthe upper die 41 are electrically connected via the bonding wires 47 tothe left-outer leads 23LO, the left-inner leads 23LI, the right-outerleads 23RO, and the right-inner leads 23RI. An encapsulant 24 is thenmolded to enclose the upper die 41, the lower die 43, the left-outerleads 23LO, the left-inner leads 23LI, the right-outer leads 23RO, andthe right-inner leads 23RI.

[0007] The foregoing patent allows two integrated circuit chips ofdifferent purposes, for example a microprocessor chip and a memory chip,to be packed in the same integrated circuit package. Moreover, sinceeach integrated circuit chip is attached on the leads of the leadframe,it can help reduce the jointed area between the integrated circuit chipand the leads; and as a result, delamination between the integratedcircuit chip and the leads can be prevented under temperature changeconditions. One drawback to the forgoing patent, however, is that thelower die 43 should be greater in size than the upper die 41 (see FIGS.9 and 10) so as to allow the left side 43L and the right side 43R of thelower die 43 to extend into the left slot 26L and the right slot 26R forthe purpose of positioning the bonding pads 43LP and 43RP in the leftslot 26L and the right slot 26R to facilitate the wire-bonding process.For this reason, the foregoing patent is only suitable for use in TYPEII integrated circuit packages, which is the type whose outer leads arearranged on the longer sides of the integrated circuit package, and isunsuitable for use in TYPE I integrated circuit packages, which is thetype whose outer leads are arranged on the shorter sides of theintegrated circuit package. The flash memory chip is typically andsuitably encapsulated a TYPE I integrated circuit package. Therefore,the fore-going patent cannot be used to pack two integrated circuitchips of which at least one is a flash memory chip to provide a doubledstorage capacity from a single integrated circuit package. Still onemore drawback to the foregoing patent is that the jointed area betweeneach integrated circuit chip and the leads of the leadframe is stillconsidered large.

SUMMARY OF THE INVENTION

[0008] It is therefore an objective of this invention to provide adual-chip integrated circuit package and a method of manufacturing thesame, which can be used to pack two integrated circuit chips of variousrelative sizes.

[0009] It is another objective of this invention to provide a dual-chipintegrated circuit package and a method of manufacturing the same, whichis suitable for use to pack flash memory chips.

[0010] It is still another objective of this invention to provide adual-chip integrated circuit package and a method of manufacturing thesame, which can be manufactured through the use of conventionalequipment and processes without having to use new ones.

[0011] In accordance with the foregoing and other objectives, theinvention proposes a new dual-chip integrated circuit package and amethod of manufacturing the same.

[0012] The dual-chip integrated circuit package of the inventionincludes the following constituent parts: (a) a leadframe having a firstset of leads and a second set of leads, the first and second sets ofleads being each defined into an inner part and an outer part, with aspacing being defined between the inner part of the first set of leadsand the inner part of the second set of leads; (b) a first integratedcircuit chip having a first side where at least one row of bonding padsare formed and a second side insulatively attached to a first side ofthe inner part of the first set of leads; (c) a second integratedcircuit chip having a first side where at least one row of bonding padsare formed, with part of the first side being insulatively attached to asecond side of the inner part of the first set of leads in such a manneras to allow the bonding pads on the second integrated circuit chip to bepositioned in the spacing; (d) a first set of bonding wires forelectrically connecting the bonding pads on the first integrated circuitchip to selected part of the leads; (e) a second set of bonding wiresfor electrically connecting the bonding pads on the second integratedcircuit chip to selected part of the leads; and (f) an encapsulant forencapsulating the first integrated circuit chip, the second integratedcircuit chip, the first set of bonding wires, the second set of bondingwires, the inner part of the first set of leads, and the inner part ofthe second set of leads.

[0013] The first integrated circuit chip can be the type that is formedwith only one row of bonding pads, such as flash memory chips, or thetype that is formed with two rows of bonding pads, such as DRAM and ASICchips. In the case of two rows, they are electrically connectedrespectively to the inner part of the first set of leads and the innerpart of the second set of leads. The second integrated circuit chip,however, can be only the type formed with one row of bonding pads, whichare electrically connected via the second set of bonding wires to theinner part of the first set of leads and/or the inner part of the secondset of leads.

[0014] It is characteristic feature of the invention that the secondintegrated circuit chip is unaligned to the first integrated circuitchip in such a manner that the second integrated circuit chip has onepart extending into the spacing between the inner part of the first setof leads and the inner part of the second set of leads to allow thebonding pads thereon to be positioned in the spacing. This unalignedchip arrangement allows no restriction to the relative sizes between thetwo integrated circuit chips, thus allowing flexible selection for thecombination of the two integrated circuit chips.

BRIEF DESCRIPTION OF DRAWINGS

[0015] The invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

[0016]FIG. 1 shows a schematic top view of a first preferred embodimentof the dual-chip integrated circuit package according to the invention;

[0017]FIG. 2 shows a schematic sectional view of the dual-chipintegrated circuit package of FIG. 1 cutting through the line 2-2;

[0018]FIG. 3 shows a schematic perspective view of the dual-chipintegrated circuit package of FIG. 1 with a part cut away to show theinside structure;

[0019]FIG. 4 is a flow diagram showing the procedural steps involved inthe method according to the invention for manufacturing the dual-chipintegrated circuit package;

[0020]FIG. 5 is a schematic sectional diagram of a second preferredembodiment of the dual-chip integrated circuit package according to theinvention;

[0021]FIG. 6 is a schematic sectional diagram of a third preferredembodiment of the dual-chip integrated circuit package according to theinvention;

[0022]FIG. 7 is a schematic sectional diagram of a fourth preferredembodiment of the dual-chip integrated circuit package according to theinvention;

[0023]FIG. 8 (PRIOR ART) shows a schematic top view of a leadframeutilized in the dual-chip integrated circuit package disclosed in U.S.Pat. No. 5,012,323;

[0024]FIG. 9 (PRIOR ART) shows a schematic top view of the integratedcircuit package of U.S. Pat. No. 5,012,323; and

[0025]FIG. 10 (PRIOR ART) shows a schematic sectional view of theintegrated circuit package of FIG. 9 cutting through the line 10-10.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026] In accordance with the invention, four embodiments are disclosedin full details in the following with reference to FIGS. 1-7.

[0027] In this specification, the terms “die” and “chip” areinterchangeable, which refer to an integrated circuit device cut from afabricated wafer.

[0028] First Preferred Embodiment (FIGS. 1-4)

[0029] The first preferred embodiment of the dual-chip integratedcircuit package according to the invention is disclosed in the followingwith reference to FIGS. 1-4.

[0030] As shown in FIGS. 1 and 2, the dual-chip integrated circuitpackage of the invention includes a leadframe 1, a first integratedcircuit chip 3, a second integrated circuit chip 5, a first set ofbonding wires 6, a second set of bonding wires 7, and an encapsulant 8.The leadframe 1 is formed with a first set of leads 10 and a second setof leads 11. The first integrated circuit chip 3 is mounted on one sideof the first set of leads 10 while the second integrated circuit chip 5is mounted on the opposite side of the same. The first set of bondingwires 6 are used to electrically connect the first integrated circuitchip 3 to the second set of leads 11; while the second set of bondingwires 7 are used to electrically connect the second integrated circuitchip 5 to the first set of leads 10. The encapsulant 8 is used toencapsulate the two integrated circuit chips 3, 5, the bonding wires 6,7, and part of the leads 10, 11 therein.

[0031] The first set of leads 10 is defined into an inner part 101 andan outer part 102, with the inner part 101 being enclosed in theencapsulant 8 and the outer part 102 being exposed to the outside of theencapsulant 8. The inner part 101 of the first set of leads 10 has afront side 103 and a back side 104. The first integrated circuit chip 3is mounted on the front side 103 of the inner part 101 of the first setof leads 10, while the second integrated circuit chip 5 is mounted onthe back side 104 of the same. Similarly, the second set of leads 11 isdefined into an inner part 111 and an outer part 112, with the innerpart 111 being enclosed in the encapsulant 8 and the outer part 112being exposed to the outside of the encapsulant 8. A spacing 12 isdefined between the inner part 101 of the first set of leads 10 and theinner part 111 of the second set of leads 11, which allows the secondset of bonding wires 7 to pass therethrough. In accordance with theinvention, the inner part 101 of the first set of leads 10 should begreater in length than either the first integrated circuit chip 3 or theinner part 111 of the second set of leads 11, so that the spacing 12 canbe located at a distance away from the center of the leadframe 1. Theleadframe 1 is made of a conductive material, such as copper, an copperalloy, an alloy of ferrite and nickel. The first integrated circuit chip3 can be electrically coupled to an external device (not shown) via thefirst set of leads 10 and/or the second set of leads 11 of the leadframe1, while the second integrated circuit chip 5 can do the same via thefirst set of leads 10 and/or the second set of leads 11 of the leadframe1. The outer parts 102, 112 of the leads 10, 11 can be bent through atrim/form process into either a gull-wing shape, a J-like shape, or anL-like shape.

[0032] In this preferred embodiment, the two integrated circuit chips 3,5 are each a flash memory device, which is formed with only one row ofbonding pads, i.e., the first integrated circuit chip 3 is formed withone row of bonding pads 31 and the second integrated circuit chip 5 isalso formed with only one row of bonding pads 51. The bonding pads 31are formed on the front side 30 of the first integrated circuit chip 3and positioned near the spacing 12, which are used to electricallyconnect the first integrated circuit chip 3 to the inner part 111 of thesecond sets of leads 11 via the first set of bonding wires 6. The backside 32 of the first integrated circuit chip 3 is attached by means ofan insulative adhesive layer 90, such as a layer of polyimide resin orepoxy resin, on the front side 103 of the inner part 101 of the firstset of leads 10, and which is positioned in such a manner as to leave ablank area 105 on the front edge of the inner part 101 of the first setof leads 10 to serve as a wire-bonding area for the second set ofbonding wires 7. The front side 50 of the second integrated circuit chip5 has one part attached by means of another insulative adhesive layer 91on the back side 104 of the inner part 101 of the first set of leads 10,and the other part extending into the spacing 12 to allow the bondingpads 51 to be positioned within the spacing 12 so that the bonding pads51 can be conveniently connected via the second set of bonding wires 7to the inner part 101 of the first set of leads 10. This unaligned chiparrangement for the two integrated circuit chips 3, 5 allows a reduceddimension to the area of the inner part 101 of the first set of leads 10that is attached to both of the two integrated circuit chips 3, 5, sothat the invention can help eliminate the adverse effect of delaminationdue to temperature change in the encapsulating process that wouldotherwise occur in the prior art thus making the resultant integratedcircuit package more reliable in use. Moreover, since the two integratedcircuit chips 3, 5 are attached to the leads of a leadframe rather thanto a die pad, the jointed area between the chips and the leadframe canbe reduced as compared to the prior art, so that the possibility ofdelamination can be further reduced.

[0033] With the invention, there is no restriction to the relative sizebetween the first integrated circuit chip 3 and the second integratedcircuit chip 5, which means that the first integrated circuit chip 3 canbe either greater than, equal to, or less than the second integratedcircuit chip 5, provided that these two integrated circuit chips 3, 5can be fitted to the inside space defined by the integrated circuitpackage.

[0034] The bonding wires 6, 7 are made of an electrically-conductivematerial, such as gold, copper, aluminum, or an alloy of these metals.The first set of bonding wires 6 are connected between the bonding pads31 on the first integrated circuit chip 3 and the front side 113 of theinner part 111 of the second set of leads 11, while the second set ofbonding wires 7 are connected between the bonding pads 51 on the secondintegrated circuit chip 5 and the front side 103 of the inner part 101of the first set of leads 10. Since the bonding wires 6, 7 are bothconnected to the front sides 103, 113 of the leads 10, 11, thewire-bonding process can be easily carried out with conventionalequipment and process. Moreover, since the two integrated circuit chips3, 5 are oppositely attached to the inner part 101 of the first set ofleads 10, they can provide a more firm support to the wire-bondingprocess, allowing the bonding wires 6, 7 to be reliably bonded inposition. Furthermore, since the second set of bonding wires 7 areseparated by a substantial distance from the upper surface 80 of theencapsulant 8, it allows the second set of bonding wires 7 to be bondedwithout having to use the precision wire looping control, allowing themanufacture process to be less complex.

[0035]FIG. 4 is a flow diagram showing the procedural steps involved inthe method according to the invention for manufacturing the foregoingdual-chip integrated circuit package.

[0036] Referring to FIG. 4 together with FIGS. 1-3, in the first step401, a first chip-mounting process is performed to mount the secondintegrated circuit chip 5 on the back side 104 of the inner part 101 ofthe first set of leads 10 in such a manner that a part of the secondintegrated circuit chip 5 is attached by means of an insulative adhesivelayer 91 and the other part is extending into the spacing 12, allowingthe bonding pads 51 on the front side 50 of the second integratedcircuit chip 5 to be positioned in the spacing 12.

[0037] In the next step 402, without having to turn the leadframe 1upside down, a second chip-mounting process is performed to mount thefirst integrated circuit chip 3 in such a manner that the back side 32of the first integrated circuit chip 3 is attached by means of aninsulative adhesive layer 90 on the front side 103 of the inner part 101of the first set of leads 10.

[0038] In the next step 403, a first wire-bonding process is performedto bond the second set of bonding wires 7 between the bonding pads 51 onthe second integrated circuit chip 5 and the wire-bonding area 105 onthe inner part 101 of the first set of leads 10, allowing the secondintegrated circuit chip 5 to be electrically connected to the first setof leads 10. These bonding wires 7 pass through the spacing 12.

[0039] In the next step 404, a second wire-bonding process is performedto bond the first set of bonding wires 6 between the bonding pads 31 onthe first integrated circuit chip 3 and the front side 113 of the innerpart 111 of the second set of leads 11, allowing the first integratedcircuit chip 3 to be electrically connected to the second set of leads11.

[0040] Since the bonding wires 6, 7 are bonded to the front sides 103,113 of the inner parts 101, 111 of the leads 10, 11, the secondwire-bonding process needs just to coat silver on the front sides 103,113 without having to turn the leadframe 1 upside down, making theoverall manufacture process more simplified as compared to the priorart.

[0041] In the next step 405, a molding process is performed to form theencapsulant 8. During this process, since the two integrated circuitchips 3, 5 can be firmly supported by the first set of leads 10, thecombined structure of the first integrated circuit chip 3, the secondintegrated circuit chip 5, and the first set of leads 10 would not beaffected by the pressure from the encapsulation resin flow that wouldotherwise cause chip inclination and exposure of the bonding wires tothe outside.

[0042] In the next step 406, a curing process is performed on theencapsulant 8. This process is a conventional technique so descriptionthereof will not be further detailed.

[0043] In the final step 407, a trim/form process is performed on theleads 10, 11. This process is also a conventional technique sodescription thereof will not be further detailed This completes themanufacture of the dual-chip integrated circuit package of theinvention.

[0044] Second Preferred Embodiment (FIG. 5)

[0045]FIG. 5 is a schematic sectional diagram of the second preferredembodiment of the dual-chip integrated circuit package according to theinvention. For distinguishing purpose, the reference numerals in FIG. 5are appended with the letter “b”.

[0046] As shown, this embodiment differs from the previous one only inthat the two sets of bonding wires 6 b, 7 b are connected in a differentmanner; i.e., the first set of bonding wires 6 b are used toelectrically connect the first integrated circuit chip 3 b to the firstset of leads 10 b (rather than the second set of leads 11 b as in thecase of the previous embodiment), and the second set of bonding wires 7b are used to electrically connect the second integrated circuit chip 5b to the second set of leads 11 b (rather than the first set of leads 10b as in the case of the previous embodiment).

[0047] Third Preferred Embodiment (FIG. 6)

[0048]FIG. 6 is a schematic sectional diagram of the third preferredembodiment of the dual-chip integrated circuit package according to theinvention. For distinguishing purpose, the reference numerals in FIG. 6are appended with the letter “c”.

[0049] In this embodiment, the first integrated circuit chip 3 c is thetype that includes two parallel rows of bonding pads 31 c, such as anASIC chip or a DRAM chip, while the second integrated circuit chip 5 cis a flash memory chip including only one row of bonding pads 51 c. Thetwo rows of bonding pads 31 c are connected via a first set of bondingwires 6 c respectively to the inner part 111 c of the second set ofleads 11 c and to the inner part 101 c of the first set of leads 10 c,while the bonding pads 51 c are electrically connected via a second setof bonding wires 7 c to the wire-bonding area 105 c in the inner part101 c of the first set of leads 10 c.

[0050] Fourth Preferred Embodiment (FIG. 7)

[0051]FIG. 7 is a schematic sectional diagram of the fourth preferredembodiment of the dual-chip integrated circuit package according to theinvention. For distinguishing purpose, the reference numerals in FIG. 7are appended with the letter “d”.

[0052] As shown, this embodiment is mostly the same as the firstembodiment except that an additional third set of bonding wires 13 d areconnected between the inner part 101 d of the first set of leads 10 dand the inner part hid of the second set of leads 11 d for the purposeof parallel coupling the two integrated circuit chips 3 d, 5 d.

[0053] The invention has been described using exemplary preferredembodiments. However, it is to be understood that the scope of theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangements.The scope of the claims, therefore, should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements.

What is claimed is:
 1. A dual-chip integrated circuit package, whichcomprises: a leadframe having a first set of leads and a second set ofleads, the first and second sets of leads being each defined into aninner part and an outer part, with a spacing being defined between theinner part of the first set of leads and the inner part of the secondset of leads; a first integrated circuit chip having a first side whereat least one row of bonding pads are formed and a second sideinsulatively attached to a first side of the inner part of the first setof leads; a second integrated circuit chip having a first side where onerow of bonding pads are formed, with the first side being insulativelypartially attached to a second side of the inner part of the first setof leads in such a manner as to allow the bonding pads on the secondintegrated circuit chip to be positioned in the spacing; a first set ofbonding wires for electrically connecting the bonding pads on the firstintegrated circuit chip to selected part of the leads of the leadframe;a second set of bonding wires for electrically connecting the bondingpads on the second integrated circuit chip to selected part of the leadsof the leadframe; and an encapsulant for encapsulating the firstintegrated circuit chip, the second integrated circuit chip, the firstset of bonding wires, the second set of bonding wires, the inner part ofthe first set of leads, and the inner part of the second set of leads.2. The dual-chip integrated circuit package of claim 1, wherein theinner part of the first set of leads is greater in length than the innerpart of the second set of leads.
 3. The dual-chip integrated circuitpackage of claim 1, wherein the first integrated circuit chip is a flashmemory chip.
 4. The dual-chip integrated circuit package of claim 1,wherein the second integrated circuit chip is a flash memory chip. 5.The dual-chip integrated circuit package of claim 1, wherein the firstintegrated circuit chip includes two parallel rows of bonding pads onthe first side thereof, which are respectively electrically connected tothe inner part of the first set of leads and the inner part of thesecond set of leads.
 6. The dual-chip integrated circuit package ofclaim 5, wherein the first integrated circuit chip is an ASIC chip. 7.The dual-chip integrated circuit package of claim 5, wherein the firstintegrated circuit chip is a DRAM chip.
 8. The dual-chip integratedcircuit package of claim 1, wherein in the case of the second integratedcircuit chip being electrically connected via the second set of bondingwires to the inner part of the first set of leads, the first integratedcircuit chip is electrically connected via the first set of bondingwires to the inner part of the second set of leads.
 9. The dual-chipintegrated circuit package of claim 1, wherein in the case of the secondintegrated circuit chip being electrically connected via the second setof bonding wires to the inner part of the second set of leads, the firstintegrated circuit chip is electrically connected via the first set ofbonding wires to the inner part of the first set of leads.
 10. Thedual-chip integrated circuit package of claim 1, wherein in the case ofthe second integrated circuit chip being electrically connected via thesecond set of bonding wires to the inner part of the first set of leads,the first integrated circuit chip is electrically connected via thefirst set of bonding wires to both the inner part of the first set ofleads and the inner part of the second set of leads.
 11. The dual-chipintegrated circuit package of claim 1, further comprising: a third setof bonding wires for electrically connecting the inner part of the firstset of leads to the inner part of the second set of leads.
 12. Thedual-chip integrated circuit package of claim 1 or 9, wherein thebonding wires are made of an electrically-conductive material.
 13. Thedual-chip integrated circuit package of claim 1, wherein theelectrically-conductive material is selected from the group consistingof gold, copper, aluminum, and an alloy thereof.
 14. The dual-chipintegrated circuit package of claim 1, wherein the first integratedcircuit chip is greater in size than the second integrated circuit chip.15. The dual-chip integrated circuit package of claim 1, wherein thefirst integrated circuit chip is equal in size to the second integratedcircuit chip.
 16. The dual-chip integrated circuit package of claim 1,wherein the first integrated circuit chip is smaller in size than thesecond integrated circuit chip.
 17. The dual-chip integrated circuitpackage of claim 1, wherein the first and second integrated circuitchips are insulatively attached to the first and second sides of theinner part of the first set of leads by means of an insulative adhesivelayer.
 18. A method for manufacturing a dual-chip integrated circuitpackage, comprising the steps of: preparing a leadframe having a firstset of leads and a second set of leads, the first and second sets ofleads being each defined into an inner part and an outer part, with aspacing being defined between the inner part of the first set of leadsand the inner part of the second set of leads; mounting a firstintegrated circuit chip and a second integrated circuit chip on oppositesides of the inner part of the first set of leads, the first integratedcircuit chip having a front side where at least one row of bonding padsare formed and a back side insulatively attached to a first side of theinner part of the first set of leads; and the second integrated circuitchip having a front side where one row of bonding pads are formed, withthe front side being insulatively partially attached to a second side ofthe inner part of the first set of leads in such a manner as to allowthe bonding pads on the second integrated circuit chip to be positionedin the spacing; performing a first wire-bonding process to bond a firstset of bonding wires to electrically connect the bonding pads on thefirst integrated circuit chip to the inner part of selected set ofleads; performing a second wire-bonding process to bond a second set ofbonding wires to electrically connect the bonding pads on the secondintegrated circuit chip to the inner part of selected set of leads; andperforming a molding process to form an encapsulant for encapsulatingthe first integrated circuit chip, the second integrated circuit chip,the first set of bonding wires, the second set of bonding wires, theinner part of the first set of leads, and the inner part of the secondset of leads.
 19. The method of claim 18, wherein the inner part of thefirst set of leads is greater in length than the inner part of thesecond set of leads.